1. Field of the Invention
The present invention relates to an address decoder circuit for a non-volatile memory and, more particularly, to an address decoder circuit which is capable of carrying out electrical erasure by applying a negative voltage to the control gate of a floating-gate type non-volatile memory and thereby injecting positive holes into its floating gate.
The invention also relates to an address decoder circuit which comprises load means and MOS transistors fed with address signals and receives a variable supply voltage whose absolute value in a writing operation is greater than that in a reading operation.
The invention further relates to a voltage supply circuit and, more particularly, to a circuit for selectively outputting, in response to a control signal, a first voltage used for a writing operation or a second voltage used for a reading or standby operation.
2. Description of the Prior Art
An address decoder circuit for use in an electrically rewritable memory such as EPROM (electrically programmable read-only memory) or E.sup.2 PROM (electrically erasable and programmable read-only memory) has three output levels including a high voltage (10 to 30 volts), an intermediate voltage (5 volts) and a reference potential (0 volt) in comparison with an address decoder circuit for some other memory such as static RAM, dynamic RAM or the like. And another feature thereof is the necessity of preparing, for execution of a test, an entire selection mode (where entire outputs are at a high level) or an entire non-selection mode (where entire outputs are at a low level).
There are presently existent great demands for reducing the number of component elements in the address decoder circuit of an EPROM or E.sup.2 PROM, particularly in that of an EPROM. The reason for such demands is based on the fact that, in the case of any EPROM where one transistor cell has a capacity of 1M bits, it becomes necessary to dispose one-row decoder circuit within a length of 4 to 5 microns. A consideration will now be given below with regard to the history of the progress in high integration of the address decoder circuit for such EPROM or E.sup.2 PROM. FIG. 5 shows a conventional address decoder circuit introduced as a known example in the Japanese Patent Publication No. 63 (1988)-22396. In this circuit diagram, Ql-Qn denote n-channel address input MOS transistors connected in series with one another to receive address signals Al-An as input signals respectively. One end of such series circuit (source of MOS transistor Ql) is grounded. Denoted by Ql is a p-channel load MOS transistor whose source and base gate are connected to the terminal of a power source Vcc and whose drain is connected to the other end (drain of MOS transistor Qn) of the series circuit consisting of the address input MOS transistors Ql-Qn. The node thereof serves as an output point of the decoding portion (logic gate portion) of the address decoder circuit, and the signal outputted therefrom is fed via an n-channel MOS transistor Qt, which functions as a transfer gate, to a buffer circuit Bu consisting of a MOS inverter. The buffer circuit Bu operates at a high supply voltage (write voltage) Vpp of, e.g. 10 to 30 volts during a write mode or at a normal supply voltage Vcc of, e.g. 5 volts during any other mode. Denoted by Qf is a p-channel pullup MOS transistor whose source and back gate receive the write voltage Vpp during a write mode or the normal supply voltage Vcc during any other mode. Its gate electrode receives the output of the buffer circuit Bu, while its drain is connected to the input of the buffer circuit Bu. The MOS transistor Qt serving as a transfer gate prevents flow of a great current from the variable power terminal (Vpp/Vcc) via the MOS transistor Qf and the load MOS transistor Ql to the normal-voltage power terminal (Vcc). Another conventional address decoder circuit so contrived as to eliminate the necessity of such MOS transistor Qt is introduced as an improved invention relative to the application of the aforementioned Japanese Patent Publication No. 63 (1988)-22396, which is shown in FIG. 6. According to this address decoder circuit, the back gate of the load MOS transistor Ql is connected to the variable power terminal (Vpp/Vcc) instead of the normal power terminal (Vcc), and the gate electrode is connected to the drain of the load MOS transistor Ql without being grounded. Due to such arrangement, even when the input side of the buffer Bu is turned to the level of a write voltage Vpp during a write mode by the pullup MOS transistor Qf, both the back gate and the gate electrode of the load MOS transistor Ql are turned to the level of its write voltage Vpp, and the potential difference between the back gate and the gate electrode is rendered zero while the gate-source voltage of the load MOS transistor Ql is reduced to zero. [In case the transistor Ql is so driven that the current flows therein in the inverse direction as in this example, it follows that the region (usually the drain of the transistor Ql connected to the address input n-channel MOS transistor) functions as a source, not as a drain.] Consequently, the load MOS transistor Ql serving as an enhancement-mode MOS transistor is cut off to prevent flow of wasteful current from the variable power terminal to the normal power terminal. Therefore the MOS transistor Qt used as a transfer gate is rendered unnecessary to eventually reduce the number of required elements at a rate of one per address decoder circuit. In view of this point, the address decoder circuit of FIG. 6 is superior to the former example of FIG. 5.
FIG. 7 shows another conventional address decoder circuit formed into a further compact constitution, which is introduced in "1955 ISSCC Digest", pp. 166-167. In this address decoder circuit, the output of the circuit consisting of address input MOS transistors Ql-Qn and a load MOS transistor Ql is fed directly to a buffer Bu, and a depression-mode MOS transistor Qt is interposed between the buffer Bu and a word line WL of a memory cell array. And a polysilicon p-channel MOS transistor is interposed between the variable power terminal (Vpp/Vcc) and the word line WL. Both the MOS transistor Qt and the polysilicon MOS transistor receive, at the gate electrodes thereof, a signal obtained by inverting a program signal PGM. In such known address decoder circuit, the buffer Bu is not connected to the variable power terminal but is so connected as to receive the supply voltage from the normal power terminal Vcc. And a writing operation is performed via the polysilicon p-channel MOS transistor.
Although such address decoder circuit is superior as viewed from high integration density, it needs a depression-mode MOS transistor Qt to consequently require one additional mask with another disadvantage of a numerical increase in the steps of manufacture, hence raising a problem of increased production cost. Furthermore, the polysilicon MOS transistor used to perform a writing operation comes to have a greater on-resistance to eventually bring about an impediment in attaining an enhanced faster operation.
FIG. 8 shows another conventional address decoder circuit where a variable supply voltage Vpp/Vcc is applied to a logic gate portion consisting of address input MOS transistor Ql-Qn and a load MOS transistor Ql. This example is introduced in "1988 ISSCC Digest", pp. 120-121. According to the above, the source of the load MOS transistor Ql is connected to the variable power terminal (Vpp/Vcc) in the same manner as the power terminal of the buffer Bu, so that there occurs no potential difference between the two power terminals. Consequently, the provision of a transfer gate is not necessary. Furthermore, since the pullup function can be performed by the load MOS transistor Ql itself, there is no need of providing any pullup MOS transistor either. Therefore the address decoder circuit shown in FIG. 8 requires the least number of component elements to eventually realize the greatest integration density.
However, any of the known address decoder circuits described above is incapable of carrying out electrical erasure to a non-volatile memory. As it has been considered heretofore that electrical erasure is impossible for the EPROM, such erasure is executed customarily by irradiation of ultraviolet rays.
The present inventor previously accomplished an improved non-volatile memory capable of carrying out electrical erasure even with the same constitution as that of an EPROM (as already filed in Japanese Patent Application No. 62 (1987)-318172). The feature of the above invention resides in injection of positive holes into a floating gate for erasure by applying a negative voltage to a control gate. The principle of the erasing operation is based on that, when a negative voltage is applied to the control gate, the withstand voltage of the gated junction is lowered, and application of a drain voltage in such state causes breakdown in the vicinity of the drain immediately below the floating gate. Then the holes resulting from such breakdown are injected into the floating gate by the electric field generated due to the negative voltage applied to the control gate, whereby desired erasure is carried out. And according to the above invention, there are attainable a variety of advantages including that bit-by-bit erasure is rendered possible by applying a negative voltage merely to one word line WL (selected word line) alone. Consequently, there can be predicted requirements for developing an improved EPROM address decoder circuit so contrived as to execute electrical erasure. The address decoder circuit adapted to meet such requirements was accomplished by the present inventor and disclosed in the specification with the accompanying drawing (FIG. 3) attached to the above application. FIG. 9 shows address input MOS transistors included in such circuit.
In FIG. 9, Q4-Q7 denote N-channel address input MOS transistors to receive address signals, and Q8 denotes a P-channel MOS transistor serving as load means for the transistors Q4-Q7. An output signal V.sub.N1 of a decoding portion consisting of the transistors Q4-Q8 is inverted by a CMOS inverter consisting of transistors Q9 and Q10, and then is transmitted to a word line WL via a MOS transistor Q11 and a transfer P-channel MOS transistor Q1. The transistor Q11 driven by an inverted signal of an erase signal Erase and is turned off during an erase mode but is turned on to conduct during any other operation mode. Denoted by Q12 is a MOS transistor connected between the node of the transistors Q11, Q1 and the output point of the decoding portion consisting of the transistors Q4-Q8. This transistor Q12 is driven by the erase signal Erase in a manner to be turned on during an erase mode and serves to invert the logic of a voltage V.sub.N2.
There are also shown transistors Q14 and Q15 which constitute a CMOS inverter for inverting the voltage V.sub.WL of the word line WL, wherein the output of such CMOS inverter is applied to the gate of a P-channel MOS transistor Q13 connected between a variable power terminal (Vpp/Vcc) and the word line WL. The circuit consisting of Q13-Q15 selectively switches the voltage of the word line WL to Vpp during a write mode or to Vcc during a read mode.
There are further shown transistors Q2 and Q3 to constitute a charge pump for generating a negative voltage, and a capacitor C1 for the same purpose. The earth terminal of the charge pump is grounded via a MOS transistor Q16 driven by the erase signal Erase. Denoted by NORl is a nor circuit which receives an erase pulse at one input terminal thereof while receiving the voltage V.sub.WL of a word line WL at the other input terminal thereof, and its output terminal is connected to one end of the capacitor C1 partially constituting the charge pump. Strictly speaking, FIG. 9 also includes a negative voltage generator circuit in addition to the address decoder circuit.
Table 1 shown below represents the voltages attained at the nodes in individual operation modes.
TABLE 1 ______________________________________ Read Write Erase Sel Non-sel Sel Non-sel Sel Non-sel ______________________________________ Vpp/Vcc 5 V 5 V Vpp Vpp 5 V 5 V V.sub.N1 0 V 5 V 0 V 5 V 0 V 5 V V.sub.N2 5 V 0 V Vpp 0 V 0 V 5 V V.sub.WL 5 V Vthp Vpp Vthp .theta. 5 V Source 0 V 0 V 0 V 0 V F1 F1 Erase 0 V 0 V 0 V 0 V 5 V 5 V ______________________________________
In Table 1: Sel stands for selection; Non-sel for non-selection; and Vpp/Vcc for Vpp/Vcc terminal in row. For example, Vpp is 12.5 volts, and Vcc is 5 volts. Source means that of a memory cell array; Vthp is the threshold voltage of a p-channel MOS transistor Trl; .theta. (minus sign enclosed with circle) denotes a negative voltage; and F1 means floating. A voltage of 5 volts may be used in place of the floating Fl.
In the row decoder circuit of FIG. 9, during an erase mode, the transistor Q11 is turned off while the transistor Q12 is turned on so that the logic values are inverse to those in any operation mode other than the erase mode. The voltage V.sub.N2 is set to 0 volt in a selection state or to +5 volts in a non-selection state, whereby the voltage V.sub.WL of the word line WL in the selection state can be of a negative value.
FIG. 13 shows another conventional address decoder circuit where a variable supply voltage Vpp/Vcc is applied to a logic gate portion consisting of address input MOS transistors Ql-Qn and a load MOS transistor Ql. This example is introduced in "1988 ISSCC Digest", pp. 120-121. According to the above, the source of the load MOS transistor Ql is connected to the variable power terminal (Vpp/Vcc) in the same manner as the power terminal of the buffer Bu, so that the powerful pullup function can be performed by the load MOS transistor Ql itself. It is therefore not necessary to provide any pullup MOS transistor. In addition to such non-necessity of a pullup MOS transistor, there occurs no potential difference between the power terminal for the buffer Bu and the power terminal for the load MOS transistor, so that no current comes to flow between the two power terminals. Consequently any transfer gate is not needed either. Thus, the address decoder circuit shown in FIG. 13 requires the least number of component elements and is therefore superior with regard to this point.
In a non-volatile memory such as PROM, EPROM or the like, it is necessary, during a writing operation, to apply a voltage Vpp (e.g. 12 volts) higher than a normal supply voltage Vcc (e.g. 5 volts) to a word line of a memory cell array. It is therefore customary to incorporate in the non-volatile memory a voltage supply circuit which receives both voltages Vcc and Vpp and selectively outputs Vpp during a write mode or outputs Vcc in any other operation mode such as a read mode or a standby mode.
FIG. 18 shows a first conventional example of such voltage supply circuit, wherein, when outputting the writing supply voltage Vpp, it is boosted by means of a voltage multiplier and then is outputted via a MOS transistor Qa. This technique is disclosed in William ip et al., "256 Kb CMOS EPROM", ISSCC 84 DIGEST, pp. 138-139 (particularly FIG. 2 thereof). Multiplying the supply voltage Vpp is effective to avert a level reduction corresponding to the threshold voltage of the MOS transistor Qa. In the above example, a writing voltage of 17 volts is obtained by boosting a supply voltage Vpp of 12 volts. In the circuit where a reading voltage Vcc is outputted via a MOS transistor Qb, a control signal (inverted signal of a write command signal PGM) received at the gate of such MOS transistor Qb is the same in level as the supply voltage Vcc. Consequently there occurs a level reduction corresponding to the threshold voltage, and the output voltage becomes Vcc-Vth (where Vth is the threshold voltage of the MOS transistor Qb).
FIG. 19 shows a second conventional example of such voltage supply circuit, wherein a write command signal PGM is converted from the Vcc level to the Vpp level and then is applied to the gate of a MOS transistor Qa. This technique is disclosed in S. Tanaka et al., "A Programmable 256B CMOS EPROM With On Chip Test Circuits", ISSCC 84 DIGEST, pp. 148-149 (particularly FIG. 5 thereof). There are included MOS transistors Qc and Qd constituting a CMOS inverter to invert the signal PGM; a MOS transistor Qe serving as a transfer gate; CMOS transistors Qf and Qg constituting a level converter; and a pullup MOS transistor Qh. In this voltage supply circuit, the control signal PGM applied to the MOS transistor Qa is converted from the Vcc level to the Vpp level by means of a level converter, so that the switching speed can be increased. However, with regard to each of the voltages Vpp and Vcc, there occurs a level reduction corresponding to the threshold voltage of the MOS transistors Qa and Qb.
In a third conventional example of FIG. 20, MOS transistors Qa and Qb for outputting voltages. Vpp and Vcc are composed of p-channel type instead of n-channel type so as not to cause the level reduction corresponding to the threshold voltage of the MOS transistors Qa and Qb. Such technique is disclosed in Hideharu Toyomoto et al., "Fast CMOS EPROM of Low Power Consumption with Large Capacity of 138 Kbits", Mitsubishi Technical Report Vol. 59, No. 3, 1985, pp. 61-64 (particularly FIG. 4 thereof) in the above voltage supply circuit, each of the MOS transistors Qa and Qb (and n-channel MOS transistor Qb') are controlled by flip-flop circuits FF1 and FF2.
FIG. 21 shows a fourth conventional example of a voltage supply circuit, wherein a supply voltage Vpp is boosted by voltage multiplier means (charge pump) similarly to the foregoing example of FIG. 18. It is therefore possible to avert the level reduction corresponding to the threshold voltage of a MOS transistor Qa. A boosting charge pump CP driven during a read mode is disposed proximate to the gate of the MOS transistor Qb which receives a control signal and produces an output voltage Vcc. And during a read mode, the level of the control signal fed to the gate of the MOS transistor Qb is raised to be higher than the supply voltage Vcc by a value more than the threshold voltage, so that the voltage Vcc can be outputted without a level reduction corresponding to the threshold voltage.
The example of FIG. 9 represents an address decoder circuit for a PROM where electrical erasure is possible. Concerning the capability of electrical erasure, this example is different from any of those shown previously in FIGS. 5 through 8. However, this address decoder circuit still has a disadvantage that the component elements thereof are numerically great.
Differing from the foregoing examples of FIGS. 6 and 7 where the decoding portion can be constituted of the MOS transistors for the 5-volt system, the address decoder circuit of FIG. 13 is so formed that the MOS transistors Ql, Qn and so forth constituting the decoding portion are to be those for the Vpp (12-volt) system. And in the MOS transistors for the 12-volt system, as compared with those for the 5-volt system, the gate length needs to be increased to form an LDD structure.
Furthermore, since the current flowing in the load MOS transistor Ql becomes extremely great during a write mode, the channel of each of the MOS transistors constituting the decoding portion needs to be widened as compared with the address decoder circuits shown in FIGS. 5 through 7. That is, the gate-source voltage V.sub.GS of the load MOS transistor Ql is -12 volts at the variable supply voltage of 12 volts and changes to 5 volts when the supply voltage is 5 volts. Therefore, comparing the values obtained by substracting the threshold voltage (e.g. 1 volt) of the MOS transistor Ql from such gate-source voltages V.sub.GS, the ratio becomes 11:4 (12-1:5-1). Since the current flowing in the transistor Ql is substantially proportional to the square of the value obtained by subtracting the threshold voltage from the gate-source voltage V.sub.GS, the ratio of the currents flowing therein becomes 121:16. It follows that the current flowing during the writing operation reaches substantially 7.5 times the values during the reading operation. Consequently, in a selection state during the writing operation, the level needs to be lowered, by the address signal input MOS transistors Ql-Qn, at the input point of the buffer Bu charged with the current 7.5 times greater than the current in the reading operation. Therefore, the channel of each of the MOS transistors Ql-Qn must be widened several times that of each of the MOS transistors Ql-Qn shown in FIGS. 5 through 7. Otherwise the high-speed operation fails to be performed.
Consequently it becomes necessary to increase the dimensions of the MOS transistors constituting the decoding portion of the address decoder circuit shown in FIG. 13, so that the desired high integration density is not exactly attainable although the component elements may be numerically decreased.
Furthermore, an extreme increase of the current flowing in the load MOS transistor Ql during the write mode is not desirable since it brings about augment of the power consumption, as well as a rise of the low-level voltage at the input point of the buffer Bu by reason that such rise causes a leakage current in the buffer Bu.
According to the voltage supply circuit shown in FIG. 18, the control signal for the multiplied supply voltage Vpp is fed to the drain and source of the MOS transistor Qa so that the writing voltage Vpp is obtained therefrom. Consequently the desired high writing voltage Vpp can be produced without causing any level reduction of the MOS transistor Qa. However, since the load current flowing during the writing operation (current required for charging a word line) comes to directly flow in the voltage multiplier means such as charge pump, its boosting circuit needs to be formed with a great capacity and large dimensions. As a result, the power consumption in the voltage multiplier is so increased as to be nonnegligible. Thus, there exists a problem in the voltage supply circuit of FIG. 18 that the voltage multiplier must be burdened with the entirety of the load current during the writing operation. The MOS transistor Qb for outputting the reading voltage Vcc receives the supply voltage Vcc at its drain, and the signal level at the gate thereof becomes the same as the level of the supply voltage Vcc, so that the voltage outputted has a level reduction corresponding to the threshold voltage of the MOS transistor Qb as compared with the supply voltage Vcc. That is, with regard to the reading voltage Vcc, no device is prepared for the level reduction corresponding to the threshold voltage of the MOS transistor.
In the next voltage supply circuit of FIG. 19, there is not incorporated any voltage multiplier and, concerning the supply voltage Vpp, a control signal PGM inputted to the gate of the MOS transistor Qa is merely converted from the Vcc level to the Vpp level. Consequently the writing voltage outputted becomes lower than the received supply voltage Vpp by a value corresponding to the threshold voltage of the MOS transistor Qa. That is, no contrivance is existent at all for feeding a programmed supply power from an external circuit to the control gate so as to enhance the writing efficiency without causing any level reduction. With respect to the supply voltage Vcc also, there occurs a level reduction corresponding to the threshold voltage of the MOS transistor Qb.
According to another conventional voltage supply circuit shown in FIG. 20, a positive supply voltage is taken out by the use of p-channel MOS transistors Qa and Qb, so that there occurs no level reduction corresponding to the threshold voltage differently from the foregoing case of using an n-channel MOS transistor. However, this circuit has another problem that latch-up may be induced due to noise and so forth. Now this problem will be described below with reference to FIG. 22. In an EPROM where a p-type semiconductor substrate is employed, p-channel MOS transistors Qa and Qb are formed in an n-type semiconductor well. Therefore the back gates of the MOS transistors Qa and Qb are connected to the terminal having a higher potential, i.e. to the Vpp terminal. Thus, the MOS transistors Qa and Qb are so constituted as shown in FIG. 22. This diagram includes a p-type semiconductor substrate a; an n-type semiconductor well b formed selectively in the surface region of the semiconductor substrate a; and p-channel MOS transistors Qa and Qb formed in such well b.
The source of the MOS transistor Qb receives the voltage Vcc, and normally the potential thereof is lower than that of the well b where the voltage Vpp is received. However, due to some noise or supply voltage fluctuation, there may occur an occasion where the source of the MOS transistor Qb has a potential higher than that of the well b. And in case the source potential of the MOS transistor Qb becomes higher than the potential of the well b by a value corresponding to the forward voltage (0.6 to 0.7 volt) at the pn junction, it follows that a great current comes to flow in a junction diode D formed between the source and the well. Then such current triggers flow of an amplified current in a parasitic transistor Q of pnp type whose emitter, base and collector are composed respectively of the source of the MOS transistor Qb, the well b and the substrate b. The parasitic transistor Q is naturally turned on when the potential of the emitter or the MOS transistor Qb becomes higher than the potential of the base or the well b by more than the forward voltage. It follows therefore that a current comes to flow from the Vcc terminal to the ground (substrate a) corresponding to the collector of the parasitic pnp transistor. Since latch-up may be caused in the manner described, a disadvantage is existent in the voltage supply circuit of FIG. 20 where the constitution is so restricted that the power sources connected directly to external pins are spaced apart from each other by the pn junction alone between the well and its internal semiconductor region.
In a further conventional voltage supply circuit of FIG. 21, the individual charge pumps are used so as not to induce any level reduction corresponding to the threshold value of the MOS transistor with respect to each of the voltages Vpp and Vcc. As far as this point is concerned, the circuit of FIG. 8 is considered to be superior. However, there still exists a disadvantage that the charge pump for lowering the Vpp level must be burdened with the entire load current in the voltage supply circuit during the writing operation similarly to the foregoing example of FIG. 18. Meanwhile the charge pump CP for preventing a level reduction of the voltage Vcc is not in operation during a standby mode, so that the voltage Vcc outputted from the voltage supply circuit during a standby mode has a level reduction. Consequently it is unavoidable that, when the standby mode kept on relatively long is switched over to a read mode, shortage of the control voltage occurs transiently.
Thus, it has been impossible heretofore to eliminate the level reduction of the supply voltage corresponding to the threshold voltage of the MOS transistor, without bringing about instability of the operation, necessity of a voltage multiplier having a large current capacity, and increase of the power consumption.